As a result of recent development in high integration of semiconductor memory devices, a dynamic random access memory (referred to as dynamic RAM hereinafter) with a large storage capacity of, for example, 4M bits has been developed. It takes more and more time for such a dynamic RAM to be tested, as the storage capacity increases. Therefore, a dynamic RAM with a self-contained testing circuit has been developed. When such a dynamic RAM with a self-contained testing circuit is set in test mode, some identical information is simultaneously written in a plurality of bits and other information stored in a plurality of bits is simultaneously read out.
FIG. 9 is a block diagram showing a structure of a conventional dynamic RAM with a self-contained testing circuit. This dynamic RAM is disclosed in Japanese Patent Laying-Open No. S.62-250593.
Referring to FIG. 9, in a memory cell array 1, a plurality of word lines and a plurality of bit line pairs are arranged to intersect each other, at which intersections memory cells are provided. In FIG. 9, there are typically shown two word lines WL1 and WL2, one bit line pair BL and BL, a memory cell MC1 provided at the intersection of the word line WL1 and the bit line BL, and a memory cell MC2 provided at the intersection of the word line WL2 and the bit line BL. A row address buffer 2 receives external address signals A0 through An and generates internal row address signals aX0 through aXn. A column address buffer 3 receives the external address signals A0 through An and generates internal column address signals aY0 through aYn.
A row decoder 4 receives the internal row address signals aX0 through aXn-1 and selects one of the plurality of word lines according to a combination of the signals. In reading operation, pieces of information in the memory cells connected to the selected word line are each read out to the corresponding bit line pair. This results in slight electric potential differences on the respective bit line pairs. A sense amplifier 5 amplifies the slight electric potential differences on the respective bit line pairs. A column decoder 6 receives the internal column address signals aY0 through aYn-1 and selects four bit line pairs out of the plurality of bit line pairs at a time according to a combination of the signals to connect them to bus line pairs I/00 through I/03, respectively.
The four bus line pairs I/00 through I/03 are connected to a data out buffer 8 through the pre-amplifiers 7a through 7d respectively. The four bus line pairs I/00 through I/03 are also connected to a data in buffer 9. A decoder 10 receives the most significant bit of the internal row address signals aXn and the most significant bit of the internal column address signals aYn. In reading operation, the decoder 10 selects one of the output signals given by the pre-amplifiers 7a through 7d to the data out buffer 8 and applies the same to an external output terminal 11 as output data D.sub.OUT. While in writing operation, the decoder 10 selects one of the four bus line pairs I/00 through I/03 according to a combination of the internal address signals aXn and aYn to get the same to transmit input data D.sub.IN from an external input terminal 12.
A timing generating circuit 13 is responsive to a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE all of which are externally applied, for generating a test mode set signal TS and a test mode reset signal TR and other several control signals. A latch circuit 14 is responsive to the test mode set signal TS and the test mode reset signal TR for generating a test mode enable signalTE. The test mode enable signal TE is enabled (turned to "L" level) during the test mode period. The data out buffer 8 and the data in buffer 9 are set in test mode when the test mode enable signal TE is enabled.
In FIG. 10, there is shown a structure of the data-in-buffer 9. The data-in-buffer 9 comprises four input selectors 9a through 9d. In the normal reading operation, one of the input selectors 9a through 9d is made available based on output of the decoder 10. As a result, input data D.sub.IN from the external input terminal 12 are transmitted to one of the four bus line paris I/00 through I/03. Meanwhile, the mode in which normal reading and writing operations are performed is here referred to as normal mode. In test mode, all of the input selectors 9a through 9d are made available by the test mode enable signal TE. As a result, input data D.sub.IN from the external input terminal 12 are transmitted to the four bus line pairs I/00 through I/03 in parallel.
In FIG. 11, there is shown a structure of the data out buffer 8. The data out buffer 8 comprises four output selectors 8a through 8d and an output test selector 8e. One of the output selectors 8a through 8d is made available based on output of the decoder 10. As a result, one of the outputs of the four pre-amplifiers 7a through 7d is transmitted to the external output terminal 11 as output data D.sub.OUT. In test mode, the test mode enable signal TE makes all the output selectors 8a through 8d unavailable and only the output test selector 8e available. As a result, the output test selector 8e comprises, for example, an excusive NOR (EXNOR) of the outputs of the four pre-amplifiers 7a through 7d, the result of which is transmitted to the external output terminal 11.
Now, operation of the dynamic RAM in FIG. 9 will be described. FIGS. 12A and 12B are timing charts for explaining operation of the dynamic RAM in normal mode. FIG. 12A is a timing chart for read cycle, while FIG. 12B is for write cycle.
In the read cycle, after the row address strobe signal RAS is turned down to the "L" level (active state), the column address strobe signal CAS is also turned down to the "L" (active state) while the write enable signal WE is held at the "H" level (non-active state). This allows the data read out of the selected memory cells in the memory dell array 1 to be outputted to the external output terminal as output data D.sub.OUT through the bus line pairs I/00 through I/03, the pre-amplifiers 7a through 7d, and the data out buffer 8.
In the write cycle, after the row address strobe signal RAS is turned down to the "L" level, the write enable signal WE and the column address strobe signal CAS are both turned down to the "L" level. This allows the input data D.sub.IN applied to the external input terminal 12 to be written in the selected memory cells in the memory cell array 1 through the data in buffer 9 and the bus line pairs I/00 through I/03.
FIGS. 13A and 13B are timing charts for explaining operation of the dynamic RAM in test mode. FIG. 13A shows test mode set cycle, and FIG. 13B show test mode reset cycle.
In the test mode set cycle, the column address strobe signal CAS and the write enable signal WE are turned down to the "L" level before the row address strobe signal RAS is turned down to the "L" level. This enables the dynamic RAM to be set in test mode.
In the test mode reset cycle, the column address strobe signal CAS is turned down to the "L" level before the row address strobe signal RAS is turned down to the "L" level while the write enable signal WE is held at the "H" level. This releases the dynamic RAM from the test mode. In the test mode reset cycle, the row address strobe signal RAS, the column address strobe signal CAS and the write enable signal WE are generated according to the so called CAS before RAS refresh timing. In other words, the dynamic RAM is released from test mode when operated according to the CAS before RAS refresh timing.
Generally, in the dynamic RAM, data stored in the respective memory cells are being lost due to leakage current with the lapse of time. In order to prevent this, it is necessary to regularly rewrite the data in the memory cells. This is referred to as "refresh". The above mentioned "CAS before RAS refresh" is one of the refresh methods.
FIG. 14 is a block diagram showing structure of a portion of the dynamic RAM in FIG. 9 which preforms the "CAS before RAS refresh".
The row address counter 2a generates address signals cX0 through cXn-1 for refresh. A CAS before RAS identifying circuit 2b receives the row address strobe signal RAS and the column address strobe signal CAS and, when they are received at the above described "CAS before RAS" timing, activates a "CAS before RAS" identifying signal CBR (referred to simply as identifying signal CBR hereinafter). The row address buffer 2 receives the external address signals A0 through An and the address signals cX0 through cXn-1 from the row address counter 2a. During the cycle in which the identifying signal CBR is non-active, the row address buffer 2 receives the external address signals A0 through An to generate them as internal row address signals aX0 through aXn while it does not accept the address signals cX0 through cXn-1 from the row address counter 2a. On the other hand, during the cycle where the identifying signal CBR is active, the row address buffer 2 receives the address signals cX0 through cXn-1 from the row address counter 2a to generate them as internal row address signals aX0 through aXn-1 while it does not accept the external address signals A0 through An. Generally, refresh operation is performed independently of the most significant bit of the row address signals so that the bit number of the address signals cX0 through cXn-1 outputted from the row address counter 2a is less than that of the external address signals A0 through An by one bit. During a refresh period, the most significant bit of the internal row address signals aXn is fixed at the "H" level or the "L" level by the row address buffer 2.
In refresh cycle, the row decoder 4 is responsive to the internal row address signals aX0 through aXn-1 for selecting one of the plurality of word lines in the memory cell array 1. As a result, data stored in the plurality of memory cells which are connected to the selected word line are each read out on the corresponding bit line pair. The electric potential differences on the respective bit line pairs are amplified by the sense amplifier 5. Thereafter, the data on the respective bit line pairs are again written in the corresponding memory cell each.
Generally, as another refresh method for a dynamic RAM, there is one called "hidden refresh" besides the above described "CAS before RAS refresh". FIG. 15 is a timing chart of the "hidden refresh" in a dynamic RAM.
In hidden refresh cycle, as in the read cycle, after the row address strobe signal RAS is turned down to the "L" level, the column address strobe signal CAS is turned down to the "L" level while the write enable signal WE is held at the "H" level. This allows the output data D.sub.OUT read out of the memory cell array 1 to appear on the external output terminal 11. Then, while the column address strobe signal CAS is held at the "L" level, the row address strobe signal RAS is raised to the "H" level and, after a predetermining time has passed, turned down to the "L" level again. As a result, refresh operation is performed while the output data D.sub.OUT remains held at the external output terminal 11.
As shown in FIG. 15, at the time t30 when the row address strobe signal RAS is turned down to the "L" level, the column address strobe signal CAS has been already turned down to the "L" level. Therefore, also in the hidden refresh cycle, as can be seen in the "CAS before RAS refresh"]cycle, the identifying signal CBR as shown in FIG. 14 is activated. As a result, a plurality of memory cells which has been selected based on the address signals cX0 through cXn-1 from the row address counter 2a are refreshed.
Methods for simultaneously testing a plurality of bits in a dynamic RAM are disclosed in the U.S. Pat. No. 4,692,901, Japanese Patent Laying-Open No. 61-292300, the U.S. Pat. No. 4,686,456 and so on. Furthermore, a detailed description of an output method for results in test mode is made in Japanese Patent Laying-Open No. S.63-140499.
Furthermore, methods for selecting function according to timing combination of clocks applied to a dynamic RAM is disclosed in the Japanese Patent Laying-Open No. 58-222500 and the U.S. Pat. No. 4,507,761. Among others, a test mode setting method according to timing combination of the row address strobe signal RAS, the column address strobe signal CAS and the write enable signal WE is disclosed in the Japanese Patent Laying-Open No. 62-250593.
Meanwhile, for test mode reset method, for example, as disclosed in the separate volume of Nikkei Micro Device 1987, No.1, P. 146, the "CAS before RAS refresh" or the "RAS only refresh" is generally performed.
As described above, in the conventional dynamic RAM, test mode reset is performed in the "CAS before RAS refresh" cycle. As shown in FIG. 13B, the identifying signal CBR is activated in the "CAS before RAS refresh" cycle. Also in the "hidden refresh" cycle as shown in FIG. 15, the identifying signal CBR is activated. Therefore, if the "hidden refresh" cycle is performed in a test mode period, the test mode is to be reset based on the activated identifying signal CBR. This means that the "hidden refresh" cannot be performed while the test mode is maintained.